1. Field of the Invention
The present invention relates to the technology of simulating (timing analysis, waveform analysis, etc.) the verification of an operation of an electronic circuit designed by combining cells entered in advance.
2. Description of the Related Art
Recently, since there has been a strong demand to develop an electronic circuit such as a printed circuit board (PCB), an integrated circuit, etc. at a lower cost in a shorter period, the significance of the CAD (computer aided design) technology for supporting the development has been evaluated much more.
In an electronic CAD system, standardization and modeling are specifically required to design various systems without much technical knowledge. The devices or parts of the functional or logical unit of an electronic circuit, etc. are entered in the library from flip-flop (hereinafter referred to as an FF), shift register, etc. a basic gate such as a NAND, NOR, etc., and a CPU, memory, etc. are entered in the library as basic elements (cells). Therefore, the logical design can be basically set by selecting a necessary cell in the cells entered in the library, and connecting the selected cells. The cells can be connected by connecting their pins.
The result of logical design is converted into a net list (logical circuit data). The net list is described as the mutual connection of cells entered in the library. The layout design and simulation are performed using the net list.
As an analysis in the simulation, a timing analysis is done to confirm whether or not an error (malfunction, etc.) occurs by the time difference in transmitting a signal. As a timing analysis, a setup time check for confirming whether or not a timing of fetching data is too late in an FF, etc., a hold time check for confirming whether or not a timing of fetching the data is too early, etc. are carried out. Additionally, a pulse width check for confirming whether or not the waveform of a transmitted clock signal maintains the form guaranteeing the operation, etc. is carried out as a waveform analysis.
FIGS. 1A and 1B show the above mentioned timing analyses. FIG. 1A shows an example of a target circuit, and FIG. 1B is a timing chart of the operation. In these figures, it is assumed that an assignment delay model in which a characteristic delay time is assigned to each cell is adopted. As it is well-known, there also is an uncertain delay model (maximum-minimum delay model) in which a delay time has margin.
In the circuit shown in FIG. 1A, FF1 and 2 correspond to cells, and CK, DT, and Q terminals correspond to the pins of the respective cells. The pin 3 indicated by a circle inputs a clock signal, or outputs a generated clock signal (clock source). The point at which the line connected to the CK terminal of the FF1 crosses the line connecting the clock source 3 to the CK terminal of the FF2 is also processed as a pin. Tcs indicates the delay time required for the clock signal output from the clock source 3 to be input into the CK terminal of the FF1, Tct indicates the delay time required for the clock signal output from the clock source 3 to be input into the CK terminal of the FF2, and Td indicates the delay time required from the rise (rise edge) of the clock signal input into the CK terminal of the FF1 to the input of the output signal (data signal) of the Q terminal of the FF1 changing by the rise of the clock signal into the DT terminal of the FF2.
In FIG. 1B, ‘CLOCK’ indicates the clock signal output from the clock source 3. ‘FF1, CK’ indicates the clock signal input into the CK terminal of the FF1. ‘FF2, DT’ indicates the data signal input into the DT terminal of the FF2. “FF2, CK” indicates the clock signal input into the CK terminal of the FF2.
The communications of the data signal between the FF1 and FF2 operated according to the clock signal have to be synchronized with the clock signal. The problems that the data signal cannot be transmitted or received, or that the clock signal is out of cycle have to be avoided. To attain this, in the FF2, the timing of changing the data signal input into the DT terminal should not be too early, and should not be too late relative to the timing of the rise of the clock signal input into the CK terminal. That is, the difference of the timings of the clock signal and the data signal is to be in an allowable range. The setup time check (over-delay check) is carried out to confirm whether or not the timing of changing the data signal is too late, and the other hold time check (racing check) is carried out to confirm whether or not the timing of changing the data signal too early.
In FIG. 1B, Tsetup and Thold indicate the time set to confirm the timing with a certain allowance. In the equations shown in FIG. 1B, Tcs+Td−Tct+Tsetup≦τ (τ is a time set for checking a setup time based on the cycle of the clock signal) indicates the relationship in which the result of the setup time check is OK, and Tcs+Td−Tct+Thold≧0 indicates the relationship in which the result of the hold time check is OK. Ts shown in FIG. 1B indicates the skew (time lag) of the clock signal between the FF1 and FF2.
The search for the route used in the above mentioned timing analysis is carried out for each analysis or type of signal. In the route (data route) through which a data signal is carried, a route is searched for chiefly based on the delay time in the entire route by, for example, a route in which the delay time required to transmit a signal is the longest (or shortest) from among the routes of signals from the starting pin to the end pin. However, in the cells entered in the library, there are some cells (for example, selectors) which output signals depending on the situation. Therefore, in such a searching process, there can be the problem that a route which is not to be used in a timing analysis is extracted. Thus, a timing analysis cannot always be done with high precision.
On the other hand, a search for a route (clock route) through which a clock signal is transmitted has been conventionally carried out as in the search for a route through which a data signal is transmitted. However, in a setup time check or a hold time check, for example, a frequency divider for dividing the frequency of a clock signal is used for a circuit, and the combination of a clock route with a data route indicating the largest (or smallest) difference in delay time is the worst example in timing. Accordingly, there has been the problem that a clock route indicating the worst check result cannot be extracted, thereby reducing the precision in a timing analysis. This holds true with a waveform analysis.
As described above, when a timing analysis, etc. is performed with high precision, it is necessary to take all clock routes into account. However, in the current circuit design, it is normal that there are a large number of pins for branch or merge of clock signals. In such a branching or a merging operation, the route obviously increases like an exponential function, and the number of the routes becomes enormously large. Therefore, doing a timing analysis on all clock routes is not a practical method in the viewpoints of memory capacity required for a process, a processing time, etc. Thus, considering all clock routes, it is necessary to reduce the requirements for a memory capacity or shorten a processing time for a process.